[Table 82] IDD Specifications and Test Conditions @ VDD&VDDQ=1.35V+0.0405V for 12/14/16/18Gbps

Parameter	SYMBO L	Test Condition	x32 Mode				Unit	NOTES
			HC12	HC14	HC16	HC18
One Bank Activate Precharge Current	IDD0	tCK = tCK(min); tWCK = tWCK(min); tRC = tRC(min); CKE_n = LOW; DQ, DBI_n are HIGH; bank and row addresses (5 CA inputs set LOW) as defined in Table 86 with ACT command; AC timings as defined in Table 91	404	430	452	TBD	mA	1
	IPP0		14	14	15	TBD	mA	1, 2
One Bank Activate Read Precharge Current	IDD1	tCK = tCK (min); tWCK = tWCK(min); tRC = tRC(min); CKE_n = LOW; one bank activated; single read burst with 50% data toggle on each data transfer, with 4 outputs per data byte driven LOW; otherwise DQ, DBI_n are HIGH; bank, row and column addresses (5 CA inputs set LOW) as defined in Table 87 with ACT and READ commands; AC timings as defined in Table 91; IOUT = 0mA	485	520	545	TBD	mA	1
Precharge Power- down Current	IDD2P	tCK = tCK (min); tWCK = tWCK(min); all banks idle; CKE_n = HIGH; all other inputs are HIGH; PLL/DLLs are off	210	230	248	TBD	mA
Precharge Standby Current	IDD2N	tCK = tCK (min); tWCK = tWCK(min); all banks idle; CKE_n = LOW; all other inputs are HIGH	299	310	327	TBD	mA
Active Power-down Current	IDD3P	tCK = tCK (min); tWCK = tWCK(min); one bank active; CKE_n = HIGH; all other inputs are HIGH	253	260	271	TBD	mA
Active Standby Current	IDD3N	tCK = tCK (min); tWCK = tWCK(min); one bank active; CKE_n = LOW; all other inputs are HIGH	422	460	477	TBD	mA
	IPP3N		10	10	10	TBD	mA	1, 2
Read Burst Current	IDD4R	tCK = tCK (min); tWCK = tWCK(min); CKE_n = LOW; one bank in each of the 4 bank groups activated; continuous read burst across bank groups with 50% data toggle on each data transfer, with 4 outputs per data byte driven LOW as defined in Table 88; bank and column addresses (5 CA inputs set LOW) as defined in Table 88; with READ command; IOUT = 0mA	1083	1220	1292	TBD	mA
Write Burst Current	IDD4W	tCK = tCK (min); tWCK = tWCK(min); CKE_n = LOW; one bank in each of the 4 bank groups activated; continuous write burst across bank groups with 50% data toggle on each data transfer, with 4 inputs per data byte set LOW; as defined in Table 89; bank and column addresses (5 CA inputs set LOW) as defined in Table 89; with WRITE command; no data mask	1242	1470	1511	TBD	mA
Refresh Current	IDD5	tCK = tCK (min); tWCK = tWCK(min); tRFCab = tRFCab(min) as defined in Table 91; CKE_n = LOW; DQ, DBI_n are HIGH; CA inputs are HIGH	723	790	830	TBD	mA	1
	IPP5		68	77	85	TBD	mA	1, 2
Self Refresh Current	IDD6	CKE_n= HIGH; all other inputs are HIGH	150	150	150	TBD	mA
Four Bank Interleave Read Current	IDD7	tCK = tCK(min); tWCK = tWCK(min); CKE_n = LOW; one bank in each of the 4 bank groups activated and precharged at tRC(min); continuous read burst across bank groups with 50% data toggle on each data transfer, with 4 outputs per data byte driven LOW as defined in Table 90; bank, row and column addresses (5 CA inputs set LOW) as defined in Table 90; with ACT and READ/ READA commands; IOUT = 0mA	1390	1640	1679	TBD	mA
	IPP7		27	31	35	TBD	mA	1, 2

NOTE :

1) Min t_RC or t_RFCab for IDD measurements is the smallest multiple of t_CK that meets the minimum of the absolute value for the respective parameter.

2) IPP currents have the same definition as IDD except that the current on the VPP supply is measured. IPP0 test and limit is applicable for IDD0 and IDD1 conditions. IPP3N

test and limit is applicable for all IDD2X, IDD3X, IDD4X and IDD6 conditions.